1. Field of the Invention
Embodiments of the invention relate generally to devices, systems and methods for communicating data. More particularly, embodiments of the invention relate to systems, devices, and related methods of communicating data, where said systems and devices may be configured to implement an error detection/correction (EDC) process.
2. Description of Related Art
Whenever information in the form of digital data is communicated between components of a system, the possibility exists for one or more bits of data to become degraded or corrupted. Common causes for data bit communication errors include channel noise, data storage and retrieval errors, switching errors, etc. For example, when electronically communicating data via a defined communication channel (e.g., one or more signal lines, wireless frequencies, optical wavelengths, etc.), noise such as that induced by electromagnetic interference, capacitive/inductive coupling, crosstalk, etc., may corrupt one or more bits of the data. Additionally or alternatively, adverse channel conditions may introduce a time or phase delay in the data causing a sampling error at the receiving end of the communication.
Contemporary electronic systems including one or more memories (e.g., computers, portable electronics, memory systems, etc.) are examples of systems where data communication errors may cause significantly performance problems. Many of these systems use high speed buses (i.e., a collection of one or more signal lines) to communicate data. Unfortunately, the metallic wires and/or traces forming conventional signal lines are highly susceptible to noise induced data errors. That is, high speed data buses in contemporary memory systems, for example, have relatively low tolerance to noise and increasingly strict timing requirements.
Some typical approaches to the communication of data via high speed data buses in contemporary memory systems are illustrated in FIGS. 1A through 1C (collectively, “FIG. 1”). These examples are drawn to a general memory system architecture which is one example of a much broader class of systems. In FIG. 1, the memory system includes a memory controller 10 connected to a memory 11 by one or more buses. Each of the examples shown in FIG. 1 uses a different approach to the communication of read/write data, as well as related control signals, address data, etc., between the memory controller and memory.
For explanation purposes, it will be assumed that the respective memories shown in FIG. 1 include a read/write memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a flash memory. Each of these memories may be implemented using a single memory device, multiple memory devices, and/or a module operatively arranging multiple memory devices.
Referring to FIG. 1A, a memory controller 10a communicates control signals to a memory 11a via a control signal bus C/S. The control signals may include, for example, a chip select signal CS, a clock enable signal CKE, a row address select signal RAS, a column address signal CAS, a write enable signal WE, etc. Memory controller 10a also communicates address signals to memory 11a via a separate address bus ADDR. Finally, read/write data is bi-directionally communicated between memory controller 10a and memory 11a via a separate data bus DQ.
Referring to FIG. 1B, a memory controller 10b communicates command and address information to a memory 11b in one or more data packets via a command/address bus C/A. Read/write data is bi-directionally communicated between memory controller 10b and memory 11b via a data bus DQ.
Referring to FIG. 1C, a memory controller 10c communicates command and address information together with write data to a memory 11c in one or more data packets via a command/address/write data (CAWD) bus (or eCA bus). Read data is transferred from memory 11c to memory controller 10c via a data bus RD.
To enhance the reliability of data communications in memory systems like those illustrated in FIG. 1, systems often supplement the payload data with additional data used to detect or detect/correct data errors identified in the payload data. This “supplemental data” is required to perform one or more error detection/correction (EDC) processes related to the payload data within the system. The term “payload data” in this context should be broadly construed to include all data not strictly limited to supplemental data. Thus, in the examples of FIG. 1, read data retrieved from memory one or more memory cells of memory 11 or write data communicated by memory controller 10 and stored into one or more memory cells of memory 11 are ready examples of payload data. However, payload data in various systems and memory systems may alternately or additionally include header information data, timing data, channel characterization data, etc.
In the examples of FIG. 1, supplemental data may variously take the form of error detection and/or error correction code data, such as parity data, cyclic redundancy checking (CRC) code, etc. The supplemental data may be communicated from memory controller 10 to memory 11 in relation to write data, or from memory 11 to memory controller 10 in relation to read data or write verify data. Once received, the supplemental data may be used to detect errors, or detect and correct errors in the payload data. Supplemental data is said to be “derived” from payload data in the conventional sense. That is, one or more conventionally understood algorithms and/or computational processes may be applied to payload data to generate corresponding supplemental data.
Examples of error correction codes and CRC codes and various associated uses are disclosed, for example, in U.S. Pat. Nos. 5,251,215, 7,221,615, and 6,412,052, and published U.S. Patent Application Publication No. 2007-0061671, the collective subject matter of which is hereby incorporated by reference.
As noted above in relation to FIG. 1B, data, a data packet including both payload and supplemental data may be communicated between memory controller 10 and memory 11. The use of data packets is well known in the art and numerous conventional protocols exist to define data packets and control data packet communication within particular systems.
At a hardware level of the exemplary memory systems illustrated in FIG. 1, the communication of data packets, potentially including supplemental data, may be implemented using the conventional approaches illustrated in FIGS. 2A and 2B. In FIGS. 2A and 2B, a grid is used to conceptually illustrate a data frame for a desired data packet. Data frames for various data packets is typically defined in relation to one or more data lanes communicating data and in relation to a sequence of contiguous time intervals (hereafter referred to as “unit intervals, or UIs”).
In this context, the term “data lane” should be broadly construed as denoting a unique stream or sequence of data bits communicated between two components of a system, whether such data bits are continuously/non-continuously and/or synchronously/asynchronously communicated. Thus, different data lanes may be distinguished from one another within a system, or within a communication channel linking components of a system. In one example consistent with the systems shown in FIG. 1, each hardwired signal line within any one of the different buses connecting memory controller 10 and memory 11 may be said to implement a data lane. Hence, an eight (8) signal line wide bus may implement eight (8) distinct data lanes using a one-for-one correspondence between signal line and data lane. However, the term data lane is not limited to only one-for-one correspondences related to a signal line within a group of signal lines forming a bus, a transmission frequency within a group of transmission frequencies, or an optical wavelength within a group of optical transmission wavelengths, etc.
The data lanes shown in FIG. 2A are labeled LANE0 through LANE8 and the data lanes in FIG. 2B are labeled LANE0 through LANE7. Unit intervals in FIG. 2A are labeled T0 through T7, where interval T0 is a first time interval and T7 is a last time interval. Unit intervals in FIG. 2B are labeled T0 through T8, where T8 is the last time interval.
Approaches involving the communication of data packets consistent with the data frames illustrated in FIGS. 2A and 2B are commonly used in conventional memory system including DRAMs, SRAMs, and/or flash memories, where read data is retrieved from (or write data is written to) one or more memory devices via a limited number of data lanes forming a constituent communication channel. For example, in a flash memory based memory system, one page of read/write data may include 64 bits. These 64 bits of read/write data may be read from (or written to) a memory device during a number of unit intervals using a number of data lanes consistent with the defined data frame.
Referring to FIG. 2A, in a first approach, a single data lane (e.g., LANE 8) is used to sequentially and respectively transmit the supplemental data (e.g., 8 bits), while the eight remaining data lanes (e.g., LANE 0 through LANE7) are used to communicate the read/write data during the eight unit intervals of the defined data frame. Using this approach, 64 bits of payload data are communicated during the eight unit interval communication period, along with 8 additional bits of supplemental data.
One advantage to this approach is its relative simplicity in terms of timing. In particular, since each data packet is communicated during eight (8) unit intervals, this approach is compatible with the timing requirements of many conventional memory systems. However, the disadvantages of this approach include (1) a requirement for an additional data lane (i.e., the additional signal line communicating the supplemental data), and (2) a requirement that the supplemental data be calculated prior to the communication of the data packet. This second requirement creates an additional timing delay, or expanded data latency, in the communication of the data packet, because the supplemental data must be available as soon as the data packet communication begins.
Referring to FIG. 2B, in a second approach, the data packet is communicated during nine (9) unit intervals using eight (8) data lanes. Thus, the 64-bit payload data may be communicated during the first eight unit intervals and then the supplemental data may be communicated during the last (ninth) unit interval. This second approach is commonly used, for example, to transfer data between memory devices in conventional fully buffered dual in-line memory modules (FBDIMM).
In this second approach, because the supplemental data is communicated after the payload data, the supplemental data need not be computed before communication of the data packet begins. Accordingly, the second approach allows some of the computational latency associated with the supplemental data to be “hidden” behind the processes involved in communicating the read/write data. As a result, the data packet may be communicated during a relatively shorter time period, as compared with the first approach. However, because the second approach communicates data during nine unit intervals instead of eight under the foregoing assumptions, the timing requirements associated with communication of the data packet in the second approach may be incompatible with existing systems. That is, where a legacy memory system expects to receive a complete data packet during eight unit intervals, the communication of the data packet over nine unit intervals mandates some timing accommodations be made in the transmission and/or receipt of the data packet. As a result of this incompatibility issue, a more complicated clocking scheme is required to implement the second approach as compared with the first approach.
Based on the foregoing, it can be seen that conventional approaches to the communication of data packets in various systems involves significant tradeoffs between data communication simplicity, timing compatibility, protocol definitions, data latency considerations, etc.